The present invention relates to a PFC (Power Factor Correction) power supply unit, and a control circuit and a control method used in the same. The present invention particularly relates to a switching power supply unit which converts an AC input from an AC power supply into a DC output with a high power factor.
As known well, AC power includes active power, reactive power and apparent power. Only power which can be converted in AC/DC conversion is the active power. Therefore, it can convert more power into DC as the power factor is higher (closer to 100%). For this reason, PFC (Power Factor Correction) is normally conducted when designing a switching power supply unit.
FIG. 11 is a diagram showing the configuration of a typical PFC converter. FIG. 11 shows the configuration of a PFC boost converter which controls a stable output voltage while creating an input current proportional to an input voltage by means of a booster circuit. In the boost converter shown in FIG. 11, the reference sign Vac designates an AC power supply; Vi, an input voltage obtained by cutting noise out of Vac by means of a filter and then performing full-wave rectification thereupon; L1, an inductor; Q1, a switching device; D1, a backflow prevention diode; Vo, an output voltage; Rload, a load; C1, an input-side smoothing capacitor; and C2, an output capacitor composed of an electrolytic capacitor. In this case, control systems for controlling the switching device Q1 can be classified into a discontinuous (current) system, a continuous (current) system and a critical system in accordance with a current following into the inductor L1. Here, the critical system is a system located in the border between the discontinuous (current) system and the continuous (current) system. The critical system is a system in which the switching device Q1 is changed over from OFF to ON as soon as the current flowing into the inductor L1 reaches zero.
As compared with the continuous (current) system, the critical system has a feature that the diode D1 has no reverse recovery current though the inductor L1 has a high peak current. The critical system is often applied to lower power supplies of 75 W to 350 W among power supplies with input power of 75 W or greater, to which PFC is obliged to be applied by regulations on higher harmonics.
As for a control method for achieving critical PFC, there have been heretofore known two methods for detecting a critical point (which is the timing when inductor discharge is completed, that is, a timing when an inductor current reaches zero). One is a system (drain voltage detection system) which uses an auxiliary winding to detect a drain voltage. The other is a system (minus current detection system) which uses a resistor to detect a minus current.
FIG. 12 shows a conventional type critical PFC converter 2 with a drain voltage detection system. The critical PFC converter 2 has a zero current detection circuit 4, an error amplifier 5 and an ON time generator 6. The zero current detection circuit 4 monitors a voltage obtained from an auxiliary wiring L2 and detects a zero current. The zero current detection circuit 4 informs the ON time generator 6 of the detection of the zero current. Further, the zero current detection circuit 4 generates a (switch) ON signal at the timing when the zero current is detected, and supplies the ON signal to a driving circuit 7. The error amplifier 5 amplifies a difference between a voltage obtained by dividing an output voltage Vo by resistors R11, R12 and a reference voltage Vref, and outputs the amplified difference as an error signal Comp.
The ON time generator 6 generates an ON width (time width in which a switching device Q1 is ON) from a zero current detection signal of the zero current detection circuit 4 and the error signal Comp of the error amplifier 5. The ON time generator 6 generates a turn-off timing from the generated ON width and outputs a (switch) OFF signal at the generated timing. The (switch) ON signal outputted from the zero current detection circuit 4 and the (switch) OFF signal outputted from the ON time generator 6 are supplied to the driving circuit 7. Based on the (switch) ON signal and the (switch) OFF signal, the driving circuit 7 controls a gate of the switching device Q1 so as to achieve a critical control operation. In the circuit configuration shown in FIG. 12, the configuration of a preliminary stage which should be located preliminary to an input voltage Vi as shown in FIG. 11 is not shown. Examples of such power supply circuits for detecting a zero cross using an auxiliary winding are shown in Patent Document 1 (Japanese Unexamined Patent Application Publication No. JP-A-2006-296158) and Patent Document 2 (Japanese Unexamined Patent Application Publication No. JP-A-2002-176768).
On the other hand, a conventional critical PFC converter 3 with a minus current detection system shown in FIG. 13 has a zero current detection circuit 4′. The zero current detection circuit 4′ is provided with a current detection resistor R13 for detecting a minus current flowing into an inductor L1. Based on the detected minus current, the zero current detection circuit 4′ detects a zero current. The other configuration is the same as the configuration shown in FIG. 12, and description thereof will be therefore omitted. An example of such a power supply circuit for detecting a zero cross using a current detection resistor is shown in Patent Document 3 (Japanese Unexamined Patent Application Publication No. JP-A-2000-324809).
In the conventional circuit configuration with the drain voltage detection system shown in FIG. 12, the auxiliary winding L2 is required. Therefore, the configuration of the inductors L1, L2 is complicated. Further, short-circuit protection for the auxiliary winding L2 is also required to make it difficult to lower the cost of the PFC converter and reduce the profile thereof.
In the conventional circuit configuration with the minus current detection system shown in FIG. 13, the auxiliary winding in the circuit configuration shown in FIG. 12 is not required. However, the following problems have been pointed out.    (1) The converter works continuously under a high input voltage.    (2) Due to a low minus current detection level, the converter is so sensitive to noise from a current loop so that malfunction occurs easily.    (3) Power consumption increases due to the minus current detection resistor.    (4) It is difficult to establish a critical interleave.
Of the four problems, the problems (1) and (4) will be described specifically.
First, the mechanism of the problem (1) will be described. FIG. 14 shows a timing chart for the description (operation in FIG. 13). In the minus current detection system, a minus current IR is detected. As shown in FIG. 14, when the current IR reaches a threshold current value Ith or lower, the current IR is detected as a critical point. However, the threshold current value Ith is not zero through it is low. Therefore, a delay time Td is further required to turn on the switching device Q1 at a true critical point. The delay time Td depends on values of an input voltage Vi, an output voltage Vo, inductance, etc. Particularly the relationship between the delay time Td and the input voltage Vi (in FIG. 14) can be illustrated as shown in FIG. 15.
As shown in FIG. 15, the delay time increases along a J-curve as the input voltage Vi increases. For example, assume that the delay time Td is set at Td1 shown in FIG. 15 in (design of) the critical PFC converter. When the input voltage Vi is higher than a half of an output voltage Vo in this case, the delay time becomes insufficient. As a result, the switching device Q1 cannot be turned on at the true critical point, but performs continuous operation. This will be further described. A boost converter has a relationship that an output voltage Vo is higher than an input voltage Vi. Assuming that the inductance of an inductor is L, it is known that when the inductor current decreases, the inductor current decreases in a slope of (Vo−Vi)/L. Accordingly, as the input voltage Vi increases, the delay time Td increases as shown in FIG. 14. When the input voltage Vi is higher than the half of the output voltage Vo, the delay time becomes insufficient. As a result, the switching device Q1 cannot be turned on at the true critical point, but performs continuous operation.
Next, the problem (4) will be described by using a configuration in which the background-art minus current detection system has been applied to two-phase critical interleave. As shown in FIG. 16, a current flowing into a minus current detection resistor R corresponds to the sum IR(=IA+IB) of currents IA and IB flowing into inductors LA and LB respectively. As shown in the timing chart of FIG. 17 (explaining operation in FIG. 16), the current IR of the two-phase (0° and 180°) critical interleave is continuous. Therefore, the critical point cannot be detected by the current detection resistor R.
In consideration of the problems, a novel critical point detection system which is not a drain voltage detection system but can avoid the defects of the minus current detection system has been demanded as a critical point detection system to be applied to a PFC converter.
It is therefore an object of the invention to provide a power factor correction power supply unit in which a novel critical point detection system requiring no auxiliary winding as in a drain voltage detection system and having no disadvantages inherent to a minus current detection system is used for improved power factor correction.
It is another object of the invention to provide a control circuit and a control method for use in the power supply unit.
Further objects and advantages of the invention will be apparent from the following description of the invention.